High density capacitor

ABSTRACT

A method of forming a capacitor is disclosed. The method includes forming a portion of a metallization layer on a substrate, forming a via layer on the substrate, and forming a first electrode between the metallization layer and the via layer, where the first electrode is electrically connected to the metallization layer. The method also includes forming a second electrode between the metallization layer and the via layer, where the second electrode is electrically connected to the via layer, and forming a dielectric layer between the first electrode and the second electrode, where the first electrode is not electrically connected to any other conductors other than through the metallization layer, and where the second electrode is not electrically connected to any conductors other than through the via layer.

TECHNICAL FIELD

The subject matter described herein relates to a metal insulator metal(MIM) capacitor, and more particularly to a high density MIM capacitor.

BACKGROUND

The semiconductor integrated circuit industry has experienced rapidgrowth in the past several decades. Technological advances insemiconductor materials and design have produced increasingly smallerand more complex circuits. These material and design advances have beenmade possible as the technologies related to processing andmanufacturing have also undergone technical advances. In the course ofsemiconductor evolution, the number of interconnected devices per unitof area has increased as the size of the smallest component that can bereliably created has decreased.

Metal-insulator-metal (MIM) capacitors are used in many applications onan integrated circuit (IC), including for memory circuits, analogcircuits, filter circuits, and decoupling noise suppression circuits.

DESCRIPTION OF DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 illustrates a cross-sectional diagram of a semiconductorsubstrate that includes a transistor and metal-insulator-metal (MIM)capacitor according to some embodiments.

FIG. 2 illustrates a cross-sectional diagram of a metal-insulator-metal(MIM) capacitor according to some embodiments.

FIG. 3 illustrates a plan view diagram of the MIM capacitor of FIG. 2according to some embodiments.

FIG. 4 illustrates a flowchart diagram of a method of forming the MIMcapacitor of FIG. 2 according to some embodiments.

FIGS. 5A-5F illustrate a method of forming the MIM capacitor of FIG. 2according to some embodiments.

When practical, similar reference numbers denote similar structures,features, or elements.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Several illustrative embodiments will now be described with respect tothe accompanying drawings, which form a part hereof. The ensuingdescription provides embodiment(s) only and is not intended to limit thescope, applicability, or configuration of the disclosure. Rather, theensuing description of the embodiment(s) will provide those skilled inthe art with an enabling description for implementing one or moreembodiments. It is understood that various changes may be made in thefunction and arrangement of elements without departing from the spiritand scope of this disclosure. In the following description, for thepurposes of explanation, specific details are set forth in order toprovide a thorough understanding of certain inventive embodiments.However, it will be apparent that various embodiments may be practicedwithout these specific details. The figures and description are notintended to be restrictive. The word “example” or “exemplary” is usedherein to mean “serving as an example, instance, or illustration.” Anyembodiment or design described herein as “exemplary” or “example” is notnecessarily to be construed as preferred or advantageous over otherembodiments or designs.

The capacitance of a MIM capacitor is related to an overlap area ofoverlapping portions of a top plate and a bottom plate of the MIMcapacitor. For a greater capacitance needed, more overlap area used. Inaddition to the overlap area, the MIM capacitor also includes anoverhead area, which is necessary for the MIM capacitor, but does notcontribute to the capacitance of the MIM capacitor. Accordingly,capacitance per area is maximized by minimizing the ratio of theoverhead area to the overlap area.

In the embodiments discussed herein MIM capacitor structures arediscussed which minimize the ratio of the overhead area to the overlaparea.

FIG. 1 illustrates a cross-sectional diagram of a semiconductorsubstrate 100, which includes a plurality of functional areas fabricatedon a single substrate. Substrate 100 includes a first area 110 and asecond area 130. First area 110 includes circuitry, such as theexemplary first transistor 112, for processing signals received from ortransmitted to, for example, second area 130, another area, or anothersystem or chip. Second area 130 also includes circuitry, such as theexemplary second transistor 132, for processing signals received from ortransmitted to, for example, first area 110, another area, or anothersystem or chip. MIM structures 140 may include a bottom electrode 142and top electrode 146, with a dielectric layer 144 sandwiched in betweenthe top and bottom electrodes 142 and 146.

The substrate may have other areas, transistors, and/or other similarMIM capacitors.

The substrate 100 also includes metallization layers and vias. Asdepicted, substrate 100 is fabricated using five metallization layers,labeled as M1 through M5, with five layers of metallization vias orinterconnects, labeled as V1 through V5. Other embodiments may containmore or fewer metallization layers and a corresponding more or fewernumber of vias. First area 110 includes a full metallization stack,including a portion of each of metallization layers M1-M5 connected byinterconnects V2-V5, with V1 connecting the stack to a source/draincontact of first transistor 112. In some embodiments, the portions ofeach of metallization layers M1-M4 extend beyond the interconnects V1-V5connected thereto by no more than a minimum distance as defined byprocess design rules.

Second area 130 includes a full metallization stack connecting MIMcapacitor 140 to a source/drain contact of second transistor 132. MIMstructures 140 are depicted as being fabricated in between the top ofthe M4 layer and the bottom the M5 layer. Also included in substrate 100is a plurality of inter-layer dielectric (ILD) layers. Six ILD layers,identified as ILD0 through ILD5 are depicted in FIG. 1 as spanning thefirst area 110 and the second area 130. The ILD layers may provideelectrical insulation as well as structural support for the variousfeatures of substrate 100 during many fabrication process steps, some ofwhich will be discussed herein.

The first and second transistors 112 and 132 may be formedsimultaneously using processing steps which substantially simultaneouslyform each of the various portions of the first and second transistors112 and 132. Similarly, interconnects V1-V5 for the first and secondareas 110 and 130 may be simultaneously formed.

In some embodiments, in the first and second areas 110 and 130, theportions of each of metallization layers M1-M4 extend beyond theinterconnects V1-V5 connected thereto by less than about 1.01 times,about 1.02 times, about 1.03 times, about 1.04 times, about 1.05 times,about 1.075 times, about 1.1 times, about 1.2 times, about 1.3 times,about 1.4 times, about 1.5 times, about 1.6 times, about 1.75 times,about 2 times, about 2.5 times, about 3 times, about 4 times, or about 5times a minimum distance as defined by process design rules. In someembodiments, the portions of each of metallization layers M1-M4 is notdirectly electrically shorted, is not directly electrically connected,and/or is not directly connected to conductors other than thoseillustrated in FIG. 1 .

The MIM capacitor 140 in FIG. 1 is connected from the top at a topelectrode 146 and from the bottom at a bottom electrode 142.

MIM capacitor 140 may be fabricated simultaneously with other MIMstructures. In some embodiments, after M4 has been patterned and ILD4has been deposited, substrate 100 undergoes a planarization process,such as chemo-mechanical planarization (CMP). After the CMP process, abottom electrode 142 is deposited overlaying ILD4 and the exposedportions of M4. The bottom electrode 142 may comprise any of a varietyof materials. For example, bottom electrode 142 may include one or moreof Pt, AlCu, TiN, Au, Ti, Ta, TaN, W, WN, and Cu. In some embodiments,other materials may be used. Generally, the bottom electrode materialsare conductive materials such as metals, certain metal nitrides, andsilicided metal nitrides. The dielectric layers ILD0 through ILD5 areformed from an insulating material, including but not limited to NiO,TiO, HfO, ZrO, ZnO, WO3, Al2O3, TaO, MoO, and CuO. In some embodiments,other materials may be used. The insulating material may be a highdielectric constant (high-k) material, which may include TiO2, Ta2O5,Y2O3, La2O5, HfO2. In some embodiments, other materials may be used. Thetop electrode 146 may be fabricated from one or more of the samematerials and/or the same thickness as bottom electrode 142, asdescribed above. In some embodiments, other materials and/or anotherthickness may be used. The one or more materials and/or the thickness ofthe top electrode 146 may be the same as the materials and/or thethickness of bottom electrode 142. In some embodiments, one or morematerials and/or the thickness of the top electrode 146 is differentfrom one or more materials and/or the thickness used for the bottomelectrode 142.

FIG. 2 illustrates a cross-sectional diagram of a metal-insulator-metal(MIM) capacitor 200 according to some embodiments. MIM capacitor 200 maybe used as MIM capacitor 140 illustrated in FIG. 1 . In alternativeembodiments, other MIM capacitors or capacitor structures may be used asMIM capacitor 140 of FIG. 1 .

MIM capacitor 200 makes an electrical connection to a section of fourthmetallization layer M4 in fourth interlayer dielectric ILD4, over whichan insulator layer 210, comprising, for example, silicon carbide, orother similar, has been formed. In some embodiments, the insulator layer210 comprises one or more other materials. The insulator layer 210 may,for example, have a thickness equal to about 10 A, about 25 A, about 50A, about 75 A, about 100 A, about 200 A, about 300 A, about 400 A, about500 A, about 600 A, about 700 A, about 800 A, about 900 A, about 1000 A,about 1100 A, about 1200 A, about 1300 A, about 1400 A, or about 1500 A.In some embodiments, the insulator layer 210 has another thickness.

MIM capacitor 200 includes a barrier layer 220 formed over the insulatorlayer 210, where the barrier layer 220 contacts the fourth metallizationlayer M4 through a hole in the insulator layer 210, as illustrated. Thebarrier layer 220 is conductive, and is configured to substantiallyprevent the metal material of fourth metallization layer M4, such ascopper, from diffusing or migrating therethrough. In some embodiments,the barrier layer 220 may, for example, be formed so as to include oneor more of Ta, TaN, and TiN. In some embodiments, other materials may beused. The barrier layer 220 may, for example, have a thickness equal toabout 10 A, about 25 A, about 50 A, about 75 A, about 100 A, about 200A, about 300 A, about 400 A, about 500 A, about 600 A, about 700 A,about 800 A, about 900 A, or about 1000 A. In some embodiments, thebarrier layer 220 has another thickness.

MIM capacitor 200 also includes a bottom electrode 230 formed over thebarrier layer 220, where the bottom electrode 230 mechanically andelectrically contacts the barrier layer 220, as illustrated. The bottomelectrode 230 is conductive, and, in some embodiments, is substantiallycoextensive with the barrier layer 220 in a lateral direction, asillustrated. In some embodiments, the bottom electrode 230 may, forexample, be formed so as to include one or more of Cu, Ag, Pt, Au, W,Ti, TiN, TaN, Ru, and Mo. In some embodiments, other materials may beused. The bottom electrode 230 may, for example, have a thickness equalto about 10 A, about 25 A, about 50 A, about 75 A, about 100 A, about200 A, about 300 A, about 400 A, about 500 A, about 600 A, about 700 A,about 800 A, about 900 A, or about 1000 A. In some embodiments, thebottom electrode 230 has another thickness.

The bottom electrode 230 and the barrier layer 220 may collectively beconsidered a bottom electrode. In some embodiments, a bottom electrodecan be considered as including one or more other conductors confined tothe peripheral boundary of bottom electrode illustrated in FIG. 3 .

MIM capacitor 200 also includes a high dielectric constant layer 240.The HK layer 240 may, for example, have a dielectric constant greaterthan about 3. In some embodiments, the HK layer provides improvedperformance because of its bandgap value. For example, the HK layer mayhave a bandgap between about 5.5 eV and about 6 eV. In some embodiments,the HK layer has a bandgap of about 5.7 eV. In some embodiments, the HKlayer has a bandgap of about 6 eV. Other bandgap values may be used. TheHK layer 240 is formed over the bottom electrode 230, where the HK layer240 mechanically contacts the barrier layer 220, as illustrated. The HKlayer 240 is insulative, and, in some embodiments, is substantiallycoextensive with the bottom electrode 230 in a lateral direction, asillustrated. In some embodiments, the HK layer 240 may, for example, beformed so as to include one or more of HfOx, TaOx, TiOx, NiOx, ZnO,Al₂O₃. In some embodiments, other materials may be used. The HK layer240 may, for example, have a thickness equal to about 5 A, about 10 A,about 25 A, about 50 A, about 75 A, about 100 A, about 200 A, about 300A, about 400 A, or about 500 A. In some embodiments, the HK layer 240has another thickness.

MIM capacitor 200 also includes a top electrode. The top electrode isformed over the HK layer 240, where the top electrode mechanicallycontacts the HK layer 240, as illustrated. The top electrode isconductive, and, in some embodiments, is smaller than the barrier layer220, the bottom electrode 230, and the HK layer 240 in a lateraldirection, as illustrated. In some embodiments, the top electrode may,for example, be formed so as to include one or more of Ta, TaN, TiN, Ni,Cu, Au, Ag, Pt. In some embodiments, other materials may be used. Thetop electrode may, for example, have a thickness equal to about 5 A,about 10 A, about 25 A, about 50 A, about 75 A, about 100 A, about 125A, about 150 A, about 175 A, about 200 A, about 300 A, about 400 A,about 500 A, about 600 A, about 700 A, about 800 A, about 900 A, orabout 1000 A. In some embodiments, the top electrode has anotherthickness.

In some embodiments, the top electrode includes one or more additionallayers. In some embodiments, one or more of the top electrode layers maybe fabricated from one or more of the same materials as one or moreothers of the top electrode layers. In some embodiments, one or morematerials of one or more of the top electrode layers may be fabricatedfrom one or more materials not used in one or more others of the topelectrode layers. In some embodiments, one or more of the top electrodelayers are coextensive in a lateral direction as one or more others ofthe top electrode layers.

In some embodiments, a top electrode can be considered as including oneor more other conductors confined to the peripheral boundary of topelectrode illustrated in FIG. 3 .

As illustrated the top electrode is surrounded by a side insulatinglayer 270, which may, for example, comprise a high dielectric material,such as SiN.

The top electrode of MIM capacitor 200 makes a mechanical and electricalconnection to a via formed in the fifth via layer V5.

FIG. 3 illustrates a plan view diagram of the MIM capacitor 200 of FIG.2 according to some embodiments. The plan view diagram of FIG. 3illustrates geometries representing peripheral boundaries of the bottomelectrode BE, the top electrode TE, and the via formed in the fifth vialayer V5.

In the illustrated embodiment, the cross-sectional view illustrated inFIG. 2 could correspond with a cross-section of the MIM capacitor 200 ina plane perpendicular to the illustrated plane of the plan view of FIG.3 and including the line segment A-A′. Similarly, in the illustratedembodiment, the cross-sectional view illustrated in FIG. 2 couldcorrespond with a cross-section of the MIM capacitor 200 in a planeperpendicular to the illustrated plane of the plan view of FIG. 3 andincluding the line segment the B-B′.

As illustrated in FIG. 2 , in this embodiment, the peripheral boundaryof the bottom electrode BE in FIG. 3 also represents peripheralboundaries of the barrier layer 220 and the HK layer 240. Similarly, asillustrated in FIG. 2 , in this embodiment, the peripheral boundary ofthe top electrode TE in FIG. 3 represents the peripheral boundary of allof the top electrode layers.

The illustrated diameter of the via is equal to the dimension D5, asillustrated in FIG. 3 . The peripheral boundary of the top electrode TEis represented as a rectangle having first and second side dimensions D1and D2. In addition, the peripheral boundary of the bottom electrode BEis represented as a rectangle having third and fourth side dimensions D3and D4.

In some embodiments, first and second side dimensions D1 and D2 are notequal. In some embodiments, first and second side dimensions D1 and D2are substantially equal, such that the peripheral boundary of the topelectrode TE substantially forms a square. In some embodiments, thirdand fourth side dimensions D3 and D4 are not equal. In some embodiments,third and fourth side dimensions D3 and D4 are substantially equal, suchthat the peripheral boundary of the bottom electrode BE substantiallyforms a square.

In the embodiment illustrated in FIG. 3 , the peripheral boundary of thebottom electrode BE and the peripheral boundary of the top electrode TEshare a common center point. In some embodiments, the peripheralboundary of the bottom electrode BE and the peripheral boundary of thetop electrode TE do not share a common center point.

In the embodiment illustrated in FIG. 3 , third side dimension D3 isgreater than first side dimension D1. Accordingly, in the embodimentillustrated in FIG. 3 , the peripheral boundary of the bottom electrodeBE extends beyond the peripheral boundary of the top electrode TE in theillustrated vertical direction. In the embodiment illustrated in FIG. 3, fourth side dimension D4 is greater than second side dimension D2.Accordingly, in the embodiment illustrated in FIG. 3 , the peripheralboundary of the bottom electrode BE extends beyond the peripheralboundary of the top electrode TE in the illustrated horizontaldirection. Accordingly, in the embodiment illustrated in FIG. 3 , theperipheral boundary of the bottom electrode BE extends beyond theperipheral boundary of the top electrode TE in all directions. In someembodiments, the peripheral boundary of the bottom electrode BE extendsbeyond the peripheral boundary of the top electrode TE by no more than aminimum distance as defined by process design rules.

In addition, in the illustrated embodiment, the peripheral boundary ofthe top electrode TE extends beyond the peripheral boundary of the viain all directions. In some embodiments, the peripheral boundary of thetop electrode TE extends beyond the peripheral boundary no more than aminimum distance as defined by a process design rules.

In some embodiments, the via is formed with a diameter dimension D5equal to about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 15 nm,about 20 nm, about 25 nm, about 30 nm, about 35 nm, about 40 nm, about50 nm, about 60 nm, about 70 nm, about 80 nm, about 90 nm, or about 100nm.

In some embodiments, the first dimension D1 is equal to about 5 nm,about 7 nm, about 10 nm, about 15 nm, about 20 nm, about 25 nm, about 30nm, about 35 nm, about 40 nm, about 50 nm, about 60 nm, about 70 nm,about 80 nm, about 90 nm, about 100 nm, about 110 nm, about 120 nm,about 130 nm, about 140 nm, about 150 nm, about 175 nm, about 200 nm, orgreater.

In some embodiments, the first dimension D1 is greater than the fifthdimension D5 by about 3 nm, about 5 nm, about 7 nm, about 10 nm, about15 nm, about 20 nm, about 25 nm, about 30 nm, about 35 nm, about 40 nm,about 50 nm, about 60 nm, about 70 nm, about 80 nm, about 90 nm, about100 nm, about 110 nm, about 120 nm, about 130 nm, about 140 nm, about150 nm, about 175 nm, about 200 nm, or more.

In some embodiments, the first dimension D1 is greater than the fifthdimension D5 by a factor, where the factor is equal to about 1.01, about1.02, about 1.03, about 1.04, about 1.05, about 1.06, about 1.08, about1.1, about 1.2, about 1.3, about 1.4, about 1.5, about 1.6, about 1.8,about 2, about 2.5, about 3, about 4, about 5, about 6, about 8, about10, about 15, about 20, about 25, about 30, about 50, about 75, about100, or more.

In some embodiments, the second dimension D2 is equal to about 5 nm,about 7 nm, about 10 nm, about 15 nm, about 20 nm, about 25 nm, about 30nm, about 35 nm, about 40 nm, about 50 nm, about 60 nm, about 70 nm,about 80 nm, about 90 nm, about 100 nm, about 110 nm, about 120 nm,about 130 nm, about 140 nm, about 150 nm, about 175 nm, about 200 nm, orgreater.

In some embodiments, the second dimension D2 is greater than the fifthdimension D5 by about 3 nm, about 5 nm, about 7 nm, about 10 nm, about15 nm, about 20 nm, about 25 nm, about 30 nm, about 35 nm, about 40 nm,about 50 nm, about 60 nm, about 70 nm, about 80 nm, about 90 nm, about100 nm, about 110 nm, about 120 nm, about 130 nm, about 140 nm, about150 nm, about 175 nm, about 200 nm, or more.

In some embodiments, the second dimension D2 is greater than the fifthdimension D5 by a factor, where the factor is equal to about 1.01, about1.02, about 1.03, about 1.04, about 1.05, about 1.06, about 1.08, about1.1, about 1.2, about 1.3, about 1.4, about 1.5, about 1.6, about 1.8,about 2, about 2.5, about 3, about 4, about 5, about 6, about 8, about10, about 15, about 20, about 25, about 30, about 50, about 75, about100, or more.

In some embodiments, the second dimension D2 is greater than the firstdimension D1 by about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10nm, about 15 nm, about 20 nm, about 25 nm, about 30 nm, about 35 nm,about 40 nm, about 50 nm, about 60 nm, about 70 nm, about 80 nm, about90 nm, about 100 nm, about 110 nm, about 120 nm, about 130 nm, about 140nm, about 150 nm, about 175 nm, about 200 nm, or more.

In some embodiments, the second dimension D2 is greater than the firstdimension D1 by a factor, where the factor is equal to about 1.01, about1.02, about 1.03, about 1.04, about 1.05, about 1.06, about 1.08, about1.1, about 1.2, about 1.3, about 1.4, about 1.5, about 1.6, about 1.8,about 2, about 2.5, about 3, about 4, about 5, about 6, about 8, about10, about 15, about 20, about 25, about 30, about 50, about 75, about100, or more.

In some embodiments, the third dimension D3 is equal to about 6 nm,about 7 nm, about 10 nm, about 15 nm, about 20 nm, about 25 nm, about 30nm, about 35 nm, about 40 nm, about 50 nm, about 60 nm, about 70 nm,about 80 nm, about 90 nm, about 100 nm, about 110 nm, about 120 nm,about 130 nm, about 140 nm, about 150 nm, about 175 nm, about 200 nm, orgreater.

In some embodiments, the third dimension D3 is greater than the fifthdimension D5 by about 4 nm, about 5 nm, about 7 nm, about 10 nm, about15 nm, about 20 nm, about 25 nm, about 30 nm, about 35 nm, about 40 nm,about 50 nm, about 60 nm, about 70 nm, about 80 nm, about 90 nm, about100 nm, about 110 nm, about 120 nm, about 130 nm, about 140 nm, about150 nm, about 175 nm, about 200 nm, or more.

In some embodiments, the third dimension D3 is greater than the fifthdimension D5 by a factor, where the factor is equal to about 1.02, about1.03, about 1.04, about 1.05, about 1.06, about 1.08, about 1.1, about1.2, about 1.3, about 1.4, about 1.5, about 1.6, about 1.8, about 2,about 2.5, about 3, about 4, about 5, about 6, about 8, about 10, about15, about 20, about 25, about 30, about 50, about 75, about 100, ormore.

In some embodiments, the third dimension D3 is greater than the firstdimension D1 by less than about 2 nm, about 3 nm, about 4 nm, about 5nm, about 7 nm, about 10 nm, about 15 nm, about 20 nm, about 25 nm,about 30 nm, about 35 nm, or about 40 nm.

In some embodiments, the third dimension D3 is greater than the firstdimension D1 by a factor, where the factor is less than about 1.01,about 1.02, about 1.03, about 1.04, about 1.05, about 1.06, about 1.08,about 1.1, about 1.2, about 1.3, about 1.4, or about 1.5.

To maximize capacitance per area used the third dimension D3 may begreater than the first dimension D1 by an amount as small as possible.

In some embodiments, the fourth dimension D4 is equal to about 6 nm,about 7 nm, about 10 nm, about 15 nm, about 20 nm, about 25 nm, about 30nm, about 35 nm, about 40 nm, about 50 nm, about 60 nm, about 70 nm,about 80 nm, about 90 nm, about 100 nm, about 110 nm, about 120 nm,about 130 nm, about 140 nm, about 150 nm, about 175 nm, about 200 nm, orgreater.

In some embodiments, the fourth dimension D4 is greater than the fifthdimension D5 by about 4 nm, about 5 nm, about 7 nm, about 10 nm, about15 nm, about 20 nm, about 25 nm, about 30 nm, about 35 nm, about 40 nm,about 50 nm, about 60 nm, about 70 nm, about 80 nm, about 90 nm, about100 nm, about 110 nm, about 120 nm, about 130 nm, about 140 nm, about150 nm, about 175 nm, about 200 nm, or more.

In some embodiments, the fourth dimension D4 is greater than the fifthdimension D5 by a factor, where the factor is equal to about 1.02, about1.03, about 1.04, about 1.05, about 1.06, about 1.08, about 1.1, about1.2, about 1.3, about 1.4, about 1.5, about 1.6, about 1.8, about 2,about 2.5, about 3, about 4, about 5, about 6, about 8, about 10, about15, about 20, about 25, about 30, about 50, about 75, about 100, ormore.

In some embodiments, the fourth dimension D4 is greater than the seconddimension D2 by less than about 2 nm, about 3 nm, about 4 nm, about 5nm, about 7 nm, about 10 nm, about 15 nm, about 20 nm, about 25 nm,about 30 nm, about 35 nm, or about 40 nm.

In some embodiments, the fourth dimension D4 is greater than the seconddimension D2 by a factor, where the factor is less than about 1.01,about 1.02, about 1.03, about 1.04, about 1.05, about 1.06, about 1.08,about 1.1, about 1.2, about 1.3, about 1.4, or about 1.5.

To maximize capacitance per area used the fourth dimension D4 may begreater than the second dimension D2 by an amount as small as possible.

In some embodiments, the fourth dimension D4 is greater than the thirddimension D3 by about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10nm, about 15 nm, about 20 nm, about 25 nm, about 30 nm, about 35 nm,about 40 nm, about 50 nm, about 60 nm, about 70 nm, about 80 nm, about90 nm, about 100 nm, about 110 nm, about 120 nm, about 130 nm, about 140nm, about 150 nm, about 175 nm, about 200 nm, or more.

In some embodiments, the fourth dimension D4 is greater than the thirddimension D3 by a factor, where the factor is equal to about 1.01, about1.02, about 1.03, about 1.04, about 1.05, about 1.06, about 1.08, about1.1, about 1.2, about 1.3, about 1.4, about 1.5, about 1.6, about 1.8,about 2, about 2.5, about 3, about 4, about 5, about 6, about 8, about10, about 15, about 20, about 25, about 30, about 50, about 75, about100, or more.

As illustrated in FIGS. 2 and 3 , the bottom electrode is not directlyelectrically shorted, is not directly electrically connected, and/or isnot directly connected to any conductors outside of the lateral areadefined by the peripheral boundary of the bottom electrode. In someembodiments, the layer forming the bottom electrode is not directlyelectrically shorted, is not directly electrically connected, and/or isnot directly connected to any conductors in a plane represented by thebottom electrode illustrated in FIG. 3 . In some embodiments, the bottomelectrode is not electrically shorted to any portions of a metallizationlayer other than through the metallization layer to which the bottomelectrode is directly contacted. In some embodiments, the bottomelectrode is not electrically connected to any other electricalcomponents other than through the metallization layer to which thebottom electrode is directly contacted.

In some embodiments, a peripheral boundary of the fourth metallizationlayer M4 does not extend beyond the peripheral boundary of the bottomelectrode.

As illustrated in FIGS. 2 and 3 , the top electrode is not directlyelectrically shorted, is not directly electrically connected, and/or isnot directly connected to any conductors outside of the lateral areadefined by the peripheral boundary of the top electrode. In someembodiments, the layer or layers forming the top electrode are notdirectly electrically shorted, are not directly electrically connected,and/or are not directly connected to any conductors in a planerepresented by the top electrode illustrated in FIG. 3 . In someembodiments, the top electrode is not electrically shorted to anyportions of a metallization layer other than through the via layer V5 towhich the top electrode is directly contacted. In some embodiments, thetop electrode is not electrically connected to any other electricalcomponents other than through the via layer to which the top electrodeis directly contacted.

FIG. 4 illustrates a flowchart diagram of a method 400 of forming theMIM capacitor of FIG. 2 according to some embodiments. In someembodiments, other methods are used.

At 410, an insulator layer 210 is deposited on the fourth dielectriclayer ILD4 and the fourth metallization layer M4, as shown in FIG. 5A.In some embodiments, insulator layer 210 comprises, for example, siliconcarbide. In some embodiments, the insulator layer 210 comprises one ormore other materials. The insulator layer 210 may, for example, have athickness equal to about 5 A, about 10 A, about 25 A, about 50 A, about75 A, about 100 A, about 150 A, about 200 A, about 250 A, about 300 A,about 400 A, about 500 A, about 600 A, about 700 A, about 800 A, about900 A, about 1000 A, about 1100 A, about 1200 A, about 1300 A, about1400 A, or about 1500 A. In some embodiments, the insulator layer 210has another thickness.

At 420, the insulator layer 210 is etched, as shown in FIG. 5B. Theinsulator layer 210 is etched such that the hole is formed in theinsulator layer 210, where the hole is aligned with a section of thefourth metallization layer M4, over which the MIM capacitor 200 is to beformed. The etching of the insulator layer 210 may include aplasma-induced etching process, or another etching process known tothose of skill in the art.

At 430, layers forming the MIM capacitor 200 are formed, as shown inFIG. 5C.

A barrier layer 220 is formed over the insulator layer 210, such thatthe barrier layer 220 contacts the fourth metallization layer M4 throughthe hole etched in the insulator layer 210 at 420.

The barrier layer 220 is conductive, and is configured to substantiallyprevent the metal material of fourth metallization layer M4, such ascopper, from diffusing or migrating therethrough. In some embodiments,the barrier layer 220 may, for example, be formed so as to include oneor more of Ta, TaN, and TiN. In some embodiments, other materials may beused. The barrier layer 220 may, for example, have a thickness equal toabout 10 A, about 25 A, about 50 A, about 75 A, about 100 A, about 200A, about 300 A, about 400 A, about 500 A, about 600 A, about 700 A,about 800 A, about 900 A, or about 1000 A. In some embodiments, thebarrier layer 220 has another thickness. In some embodiments, thebarrier layer 220 is formed by one or more of chemical vapor deposition(CVD), a variety of suitable processes including CVD, low pressure CVD(LPCVD), plasma-enhanced CVD (PECVD), and atomic layer deposition (ALD).In some embodiments, other suitable processes may be used to form thebarrier layer 220.

A bottom electrode 230 is formed over the barrier layer 220, where thebottom electrode 230 mechanically and electrically contacts the barrierlayer 220, as illustrated in FIG. 5C. The bottom electrode 230 isconductive, and may, for example, be formed so as to include one or moreof Cu, Ag, Pt, Au, W, Ti, TiN, TaN, Ru, and Mo. In some embodiments,other materials may be used. The bottom electrode 230 may, for example,have a thickness equal to about 10 A, about 25 A, about 50 A, about 75A, about 100 A, about 200 A, about 300 A, about 400 A, about 500 A,about 600 A, about 700 A, about 800 A, about 900 A, or about 1000 A. Insome embodiments, the bottom electrode 230 has another thickness. Insome embodiments, the bottom electrode 230 is formed by one or more ofchemical vapor deposition (CVD), a variety of suitable processesincluding CVD, low pressure CVD (LPCVD), plasma-enhanced CVD (PECVD),and atomic layer deposition (ALD). In some embodiments, other suitableprocesses may be used to form the bottom electrode 230.

A high dielectric constant layer 240 is formed. The HK layer 240 may,for example, have a dielectric constant greater than about 3. The HKlayer 240 is formed over the bottom electrode 230, such that the HKlayer 240 mechanically contacts the barrier layer 220, as illustrated inFIG. 5C. The HK layer 240 is insulative, and may, for example, be formedso as to include one or more of HfOx, TaOx, TiOx, NiOx, ZnO, Al₂O₃. Insome embodiments, other materials may be used. The HK layer 240 may, forexample, have a thickness equal to about 10 A, about 25 A, about 50 A,about 75 A, about 100 A, about 200 A, about 300 A, about 400 A, or about500 A. A variety of suitable processes including chemical vapordepositions (CVD), low pressure CVD (LPCVD), plasma-enhanced CVD(PECVD), and atomic layer deposition (ALD) may be used to form the HKlayer 240. In some embodiments, other suitable processes may be used toform the high dielectric constant layer 240.

A top electrode is formed. In the illustrated embodiment, the topelectrode comprises first and second top electrode layers 250 and 260.The first and second top electrode layers 250 and 260 are formed overthe HK layer 240, where the first top electrode layer 250 mechanicallycontacts the HK layer 240, and the second top electrode layer 260electrically and mechanically contacts the first top electrode layer250, as illustrated in FIG. 5C. The first and second top electrodelayers 250 and 260 are conductive, and may, for example, be formed so asto include one or more of Ta, TaN, TiN, Ni, Cu, Au, Ag, Pt. In someembodiments, other materials may be used. The first and second topelectrode layers 250 and 260 may, for example, have a combined thicknessequal to about 10 A, about 25 A, about 50 A, about 75 A, about 100 A,about 200 A, about 300 A, about 400 A, about 500 A, about 600 A, about700 A, about 800 A, about 900 A, or about 1000 A. In some embodiments,the first and second top electrode layers 250 and 260 have anothercombined thickness. A variety of suitable processes including chemicalvapor depositions (CVD), low pressure CVD (LPCVD), plasma-enhanced CVD(PECVD), and atomic layer deposition (ALD) may be used to form the firstand second top electrode layers 250 and 260. In some embodiments, othersuitable processes may be used to form the first and second topelectrode layers 250 and 260.

In some embodiments, the top electrode includes one or more additionallayers. In some embodiments, one or more of the top electrode layers maybe fabricated from one or more of the same materials as one or moreothers of the top electrode layers. In some embodiments, one or morematerials of one or more of the top electrode layers may be fabricatedfrom one or more materials not used in one or more others of the topelectrode layers. In some embodiments, one or more of the top electrodelayers are coextensive in a lateral direction as one or more others ofthe top electrode layers.

A sacrificial layer 280 is deposited on the top electrode, as shown inFIG. 5C. In some embodiments, sacrificial layer 280 comprises, forexample, SiON. In some embodiments, the sacrificial layer 280 comprisesone or more other materials. The sacrificial layer 280 may, for example,have a thickness equal to about 100 A, about 200 A, about 300 A, about400 A, about 500 A, about 600 A, about 700 A, about 800 A, about 900 A,about 1000 A, about 1100 A, about 1200 A, about 1300 A, about 1400 A, orabout 1500 A. In some embodiments, the sacrificial layer 280 has anotherthickness. In some embodiments, the sacrificial layer 280 is formed byone or more of chemical vapor deposition (CVD), a variety of suitableprocesses including CVD, low pressure CVD (LPCVD), plasma-enhanced CVD(PECVD), and atomic layer deposition (ALD). In some embodiments, othersuitable processes may be used to form the sacrificial layer 280.

At 440, layers forming the MIM capacitor 200 formed at 430 arepatterned.

Insulator layer 210, barrier layer 220, bottom electrode 230, highdielectric constant layer 240, first and second top electrode layers 250and 260, and sacrificial layer 280 are patterned, as illustrated in FIG.5D. The material of these patterned layers may be patterned using one ormore photolithography processes, maskless lithography processes, or avariety of other processes suitable for transferring a pattern to thelayers formed at 430. The patterning of each layer may be done using anynumber of combinations of material removal processes or it may beaccomplished by a single material removal process.

Insulator layer 210, barrier layer 220, bottom electrode 230, and highdielectric constant layer 240 are patterned so as to be coextensive, andso that each of the insulator layer 210, barrier layer 220, bottomelectrode 230, and high dielectric constant layer 240 has a plan viewouter peripheral boundary such as that discussed with reference to thebottom electrode of FIGS. 2 and 3 . In some embodiments, one or more orall of insulator layer 210, barrier layer 220, bottom electrode 230, andhigh dielectric constant layer 240 are patterned with the samephotolithographic processing mask.

First and second top electrode layers 250 and 260, and sacrificial layer280 are patterned so as to be coextensive, and so that each of the firstand second top electrode layers 250 and 260, and sacrificial layer 280has a plan view outer peripheral boundary such as that discussed withreference to the top electrode of FIGS. 2 and 3 . In some embodiments,one or more or all of first and second top electrode layers 250 and 260,and sacrificial layer 280 are patterned with the same photolithographicprocessing mask.

In addition, at 440, a side insulating layer 270 is formed around thetop electrode, as shown in FIG. 5D.

Side insulating layer 270 may be deposited and patterned such thatremaining portions of the side insulating layer 270 are over theinsulator layer 210, barrier layer 220, bottom electrode 230, and thehigh dielectric constant layer 240, and such that the remaining portionsof the side insulating layer 270 surround the first and second topelectrode layers 250 and 260, and sacrificial layer 280, as illustratedin FIG. 5D.

A variety of suitable processes including chemical vapor depositions(CVD), low pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), and atomiclayer deposition (ALD) may be used to form the first and second topelectrode layers 250 and 260. In some embodiments, other suitableprocesses may be used to deposit the side insulating layer 270.

Side insulating layer 270 may be patterned using one or morephotolithography processes, maskless lithography processes, or a varietyof other processes suitable for transferring a pattern to sideinsulating layer 270. In some embodiments, side insulating layer 270 ispatterned with the same photolithographic processing mask used forpatterning one or more or all of insulator layer 210, barrier layer 220,bottom electrode 230, and high dielectric constant layer 240. In someembodiments, side insulating layer 270 is patterned with the samephotolithographic processing mask used for patterning one or more or allof first and second top electrode layers 250 and 260, and sacrificiallayer 280.

In some embodiments, the side insulating layer 270, or the sideinsulating layer 270 and the sacrificial layer 280 are planarized with aplanarization process, such as chemo-mechanical planarization (CMP).

At 450, fifth interlayer dielectric ILD5 is formed over and around thelayers formed and patterned at 440, as shown in FIG. 5E. In someembodiments, the fifth interlayer dielectric ILD5 is formed by one ormore of chemical vapor deposition (CVD), a variety of suitable processesincluding CVD, low pressure CVD (LPCVD), plasma-enhanced CVD (PECVD),and atomic layer deposition (ALD). In some embodiments, other suitableprocesses may be used to form the fifth interlayer dielectric ILD5.

At 460, a via is formed in the fifth via layer V5, as shown in FIG. 5F.To form the via, fifth interlayer dielectric ILD5 is etched to form avia hole, for example, using one or more plasma-induced etchingprocesses. Other etching processes may be used. In addition, sacrificiallayer 280 is removed to extend the via hole to the second top electrodelayer 260, for example, using one or more wet etch processes, or anotheretching process. In some embodiments, the fifth interlayer dielectricILD5 and the sacrificial layer 280 are both etched during an etchingprocess. Furthermore, the via hole is filled with a suitable conductivematerial comprising, for example, one or more of copper and aluminum.

The fifth interlayer dielectric ILD5 and the fifth via layer V5 maysubsequently be planarized using, for example, a CMP planarizationprocess.

As discussed in further detail above, a MIM capacitor having high areaefficiency or capacitance/area density may be formed may limiting thearea of the bottom electrode which does not contribute to thecapacitance of the MIM capacitor.

One inventive aspect is a method of forming a capacitor. The methodincludes forming a portion of a metallization layer on a substrate,forming a via layer on the substrate, and forming a first electrodebetween the metallization layer and the via layer, where the firstelectrode is electrically connected to the metallization layer. Themethod also includes forming a second electrode between themetallization layer and the via layer, where the second electrode iselectrically connected to the via layer, and forming a dielectric layerbetween the first electrode and the second electrode, where the firstelectrode is not electrically connected to any other conductors otherthan through the metallization layer, and where the second electrode isnot electrically connected to any conductors other than through the vialayer.

In some embodiments, a peripheral boundary of the first electrodeencompasses a peripheral boundary of the portion of the metallizationlayer.

In some embodiments, a peripheral boundary of the first electrodeencompasses a peripheral boundary of the second electrode.

In some embodiments, the dielectric layer and the first electrode arecoextensive to a peripheral boundary of the first electrode.

In some embodiments, the first electrode includes first and secondbottom electrode layers.

In some embodiments, the first and second bottom electrode layers arecoextensive to a peripheral boundary of the first electrode.

In some embodiments, the second electrode includes first and second topelectrode layers.

In some embodiments, the first and second top electrode layers arecoextensive to a peripheral boundary of the second electrode.

Another inventive aspect is a method of forming a capacitor. The methodincludes forming a portion of a metallization layer on a substrate,forming a via layer on the substrate, and forming a first electrodebetween the metallization layer and the via layer, where the firstelectrode is electrically connected to the metallization layer. Themethod also includes forming a second electrode between themetallization layer and the via layer, where the second electrode iselectrically connected to the via layer, and forming a dielectric layerbetween the first electrode and the second electrode, where the firstelectrode is not electrically connected to any other electricalcomponents other than through the portion of the metallization layer,and where the second electrode is not electrically connected to anyother electrical components other than through the via layer.

In some embodiments, a peripheral boundary of the first electrodeencompasses a peripheral boundary of the portion of the metallizationlayer.

In some embodiments, a peripheral boundary of the first electrodeencompasses a peripheral boundary of the second electrode.

In some embodiments, the dielectric layer and the first electrode arecoextensive to a peripheral boundary of the first electrode.

In some embodiments, the first electrode includes first and secondbottom electrode layers.

In some embodiments, the first and second bottom electrode layers arecoextensive to a peripheral boundary of the first electrode.

In some embodiments, the second electrode includes first and second topelectrode layers.

In some embodiments, the first and second top electrode layers arecoextensive to a peripheral boundary of the second electrode.

Another inventive aspect is a capacitor, including a semiconductorsubstrate, a portion of a metallization layer formed on thesemiconductor substrate, a via layer formed on the semiconductorsubstrate, and a first electrode between the metallization layer and thevia layer, where the first electrode is electrically connected to themetallization layer. The capacitor also includes a second electrodebetween the metallization layer and the via layer, where the secondelectrode is electrically connected to the via layer, and a dielectriclayer between the first electrode and the second electrode, where thefirst electrode includes first and second bottom electrode layers, wherethe first and second bottom electrode layers are coextensive to aperipheral boundary of the first electrode, and where the secondelectrode includes first and second top electrode layers, where thefirst and second top electrode layers are coextensive to a peripheralboundary of the second electrode.

In some embodiments, a peripheral boundary of the first electrodeencompasses a peripheral boundary of the portion of the metallizationlayer.

In some embodiments, a peripheral boundary of the first electrodeencompasses a peripheral boundary of the second electrode.

In some embodiments, the dielectric layer and the first electrode arecoextensive to a peripheral boundary of the first electrode.

In the descriptions above and in the claims, phrases such as “at leastone of” or “one or more of” may occur followed by a conjunctive list ofelements or features. The term “and/or” may also occur in a list of twoor more elements or features. Unless otherwise implicitly or explicitlycontradicted by the context in which it used, such a phrase is intendedto mean any of the listed elements or features individually or any ofthe recited elements or features in combination with any of the otherrecited elements or features. For example, the phrases “at least one ofA and B;” “one or more of A and B;” and “A and/or B” are each intendedto mean “A alone, B alone, or A and B together.” A similarinterpretation is also intended for lists including three or more items.For example, the phrases “at least one of A, B, and C;” “one or more ofA, B, and C;” and “A, B, and/or C” are each intended to mean “A alone, Balone, C alone, A and B together, A and C together, B and C together, orA and B and C together.” Use of the term “based on,” above and in theclaims is intended to mean, “based at least in part on,” such that anunrecited feature or element is also permissible.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method of forming a capacitor, the methodcomprising: forming a portion of a metallization layer on a substrate;forming a via layer on the substrate; forming a first electrode betweenthe metallization layer and the via layer, wherein the first electrodeis electrically connected to the metallization layer; forming a secondelectrode between the metallization layer and the via layer, wherein thesecond electrode is electrically connected to the via layer; and forminga dielectric layer between the first electrode and the second electrode,wherein the first electrode is not electrically connected to any otherconductors other than through the metallization layer, and wherein thesecond electrode is not electrically connected to any conductors otherthan through the via layer.
 2. The method of claim 1, wherein aperipheral boundary of the first electrode encompasses a peripheralboundary of the portion of the metallization layer.
 3. The method ofclaim 1, wherein a peripheral boundary of the first electrodeencompasses a peripheral boundary of the second electrode.
 4. The methodof claim 1, wherein the dielectric layer and the first electrode arecoextensive to a peripheral boundary of the first electrode.
 5. Themethod of claim 1, wherein the first electrode comprises first andsecond bottom electrode layers.
 6. The method of claim 5, wherein thefirst and second bottom electrode layers are coextensive to a peripheralboundary of the first electrode.
 7. The method of claim 1, wherein thesecond electrode comprises first and second top electrode layers.
 8. Themethod of claim 7, wherein the first and second top electrode layers arecoextensive to a peripheral boundary of the second electrode.
 9. Amethod of forming a capacitor, the method comprising: forming a portionof a metallization layer on a substrate; forming a via layer on thesubstrate; forming a first electrode between the metallization layer andthe via layer, wherein the first electrode is electrically connected tothe metallization layer; forming a second electrode between themetallization layer and the via layer, wherein the second electrode iselectrically connected to the via layer; and forming a dielectric layerbetween the first electrode and the second electrode, wherein the firstelectrode is not electrically connected to any other electricalcomponents other than through the portion of the metallization layer,and wherein the second electrode is not electrically connected to anyother electrical components other than through the via layer.
 10. Themethod of claim 9, wherein a peripheral boundary of the first electrodeencompasses a peripheral boundary of the portion of the metallizationlayer.
 11. The method of claim 9, wherein a peripheral boundary of thefirst electrode encompasses a peripheral boundary of the secondelectrode.
 12. The method of claim 9, wherein the dielectric layer andthe first electrode are coextensive to a peripheral boundary of thefirst electrode.
 13. The method of claim 9, wherein the first electrodecomprises first and second bottom electrode layers.
 14. The method ofclaim 13, wherein the first and second bottom electrode layers arecoextensive to a peripheral boundary of the first electrode.
 15. Themethod of claim 9, wherein the second electrode comprises first andsecond top electrode layers.
 16. The method of claim 15, wherein thefirst and second top electrode layers are coextensive to a peripheralboundary of the second electrode.
 17. A capacitor, comprising: asemiconductor substrate; a portion of a metallization layer formed onthe semiconductor substrate; a via layer formed on the semiconductorsubstrate; a first electrode between the metallization layer and the vialayer, wherein the first electrode is electrically connected to themetallization layer; a second electrode between the metallization layerand the via layer, wherein the second electrode is electricallyconnected to the via layer; and a dielectric layer between the firstelectrode and the second electrode, wherein the first electrodecomprises first and second bottom electrode layers, wherein the firstand second bottom electrode layers are coextensive to a peripheralboundary of the first electrode, and wherein the second electrodecomprises first and second top electrode layers, wherein the first andsecond top electrode layers are coextensive to a peripheral boundary ofthe second electrode.
 18. The capacitor of claim 17, wherein aperipheral boundary of the first electrode encompasses a peripheralboundary of the portion of the metallization layer.
 19. The capacitor ofclaim 17, wherein a peripheral boundary of the first electrodeencompasses a peripheral boundary of the second electrode.
 20. Thecapacitor of claim 17, wherein the dielectric layer and the firstelectrode are coextensive to a peripheral boundary of the firstelectrode.